The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. In particular, the invention provides a method and system for testing the integrity of multi-level interconnect structures. More particularly, the invention provides a method and device for testing for breakdown in conductivity of an interconnect structure attributable to electromigration, but it would be recognized that the invention has a much broader range of applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process including testing limitations exist with certain conventional processes and testing procedures for wafer reliability.
As merely an example, aluminum metal layers have been the choice of material for semiconductor devices as long as such layers have been used in the first integrated circuit device. Aluminum had been the choice since it provides good conductivity and sticks to dielectric materials as well as semiconductor materials.
Most recently, aluminum metal layers have been replaced, in part, by copper interconnects. Copper interconnects have been used with low k dielectric materials to form advanced conventional semiconductor devices. Copper has improved resistance values of aluminum for propagating signals through the copper interconnect at high speeds.
As devices become smaller and demands for integration become greater, limitations in copper and low k dielectric materials include unwanted migration of Cu or other conducting materials into other portions of the integrated circuit. Accordingly, conducting copper features are typically encased within barrier materials such as silicon nitride (SiN), which impede the diffusion of the copper.
Cu dislocation at post-CMP copper surface and SiN cap is one of top killer mechanisms affecting copper backend reliability failures as well as electric failures. One example of such a failure is local bridging of two or multiple metal lines by HTOL stress.
Examples of Cu dislocation triggered by electromigration include copper mass migration, void formation during grain growth, and grain boundary reorganization. Controlling Cu dislocation is a key solution to improve reliability and yield issues due to such related fail modes.
FIG. 1A shows simplified cross-sectional view of a copper feature 2 formed within dielectric 4 and sealed by overlying silicon nitride barrier layer 6. FIG. 1A shows that the presence of topography such as hillocks 8 and voids 10 in the copper, can produce uneven thickness and passivation in the overlying SiN barrier layer. As a result, upon exposure of the copper-containing structure to the flow of charge, stress release along grain boundaries of the copper can result in unwanted migration, breaking the SiN barrier.
FIG. 1B is an electron micrograph showing a cross section of metal bridging after stress due to copper dislocation. FIG. 1B shows the electrically stressed metal lines fabricated without copper dislocation control, where bulk copper migration outside of trench is seen. This migration caused an electric short and destroyed the functionality of the die.
The sudden and catastrophic failure of the device of FIG. 1A is to be avoided. Accordingly, engineers have developed tests for estimating the amount of migration expected to occur in a device experiencing the application of a potential difference. These tests involve the application of voltage to test structures on the surface of the chip. These test structures are not intended to operate during actual functioning of the chip, but rather are present solely to allow the application of voltage to access the amount of unwanted migration that is expected to occur.
Conventionally, separate test structures have been required to evaluate the potential for migration in each conducting layer. Such multiple test structures occupy valuable real estate on the chip that is more profitably allocated to active devices.
From the above, it is seen that improved techniques and test structures for predicting the reliability of semiconductor devices is desired.